Jasper User Group India 2025

Thank you for joining us on May 28 for Jasper User Group India 2025. This interactive, in-depth technical conference connected designers, verification engineers, and engineering managers to share the latest design and verification practices based on Cadence® Jasper formal verification technologies and methodologies. In this premier industry event formal experts and beginners learned from each other how to effectively accelerate their design and validation processes by applying formal methods.

Conference highlights include:

User presentations
Poster presentations
Roadmap discussions
New technology demos
Executive keynotes
Best paper and poster presentation awards
Networking

Agenda

All Sessions

All Sessions

Agenda

Bug Hunting and Advanced Flows Track
Timing	Topic
9:00 - 9:30	Registration
9:30 - 9:45	Welcome
9:45 - 10:30	Cadence Keynote - AI Silicon Agents: Transforming the Future of Chip Design Ziyad Hanna, Corporate Vice President, R&D, *Cadence*
10:30 - 11:00	Guest Keynote - Accelerating Your Formal Verification Success with AI Ashok Kumar Natarajan, Director, Design Verification, *Google*
11:00 - 11:15	Tea Break
11:15 - 11:45	Intel Presentation - Uncovering Hardware Vulnerabilities: Formal Verification for Security-Focused Negative Testing
11:45 - 12:15	Samsung Presentation - Navigating Design Complexity Using State Space Tunneling and Robust Helper Assertions
12:15 - 12:45	Marvell Presentation - Overcoming Formal Verification Challenges in Concurrent-Linked List Hardware Designs
12:45 - 13:45	Lunch Break
13:45 - 14:15	NVIDIA Presentation - Cherry-Picking Assertions: Enhancing Convergence in CAG Using Formal Profiler
14:15 - 14:45	Google Presentation - A Formal-First Bug Hunting Approach to Verifying Transactional Integrity Under Hardware Auto Clock Gating Utilizing Q-Channel Handshakes
14:45 - 15:15	Qualcomm Presentation - Bottleneck to Breakthrough: FuSa Diagnostic Coverage with Formal Symbolic Simulator
15:15 - 15:45	Tea Break & Poster Presentations
15:45 - 16:30	Cadence Technology Shorts
16:30 - 16:45	Closing Ceremony and Awards

Left Shift and Productivity Track
Timing	Topic
9:00 - 9:30	Registration
9:30 - 9:45	Welcome
9:45 - 10:30	Cadence Keynote - AI Silicon Agents: Transforming the Future of Chip Design Ziyad Hanna, Corporate Vice President, R&D, *Cadence*
10:30 - 11:00	Guest Keynote - Accelerating Your Formal Verification Success with AI Ashok Kumar Natarajan, Director, Design Verification, *Google*
11:00 - 11:15	Tea Break
11:15 - 11:45	NVIDIA Presentation - Catching the Unseen: A Structured FV Approach for Ensuring Signoff of Complex Caching and Ordering Unit
11:45 - 12:15	Intel Presentation - Symbiotic Relation of Tool and Design: Advancing C2RTL Methodology
12:15 - 12:45	AMD Presentation - Redefining Bound Analysis: Unlocking the Power of Bounded Coverage Signoff for Complex Design Verification
12:45 - 13:45	Lunch Break
13:45 - 14:15	Qualcomm Presentation - Reducing Area and Leakage Power: Novel Formal Methodology for Retention Sufficiency in Low Power Designs
14:15 - 14:45	NXP Presentation - Application of Formal Verification Methods to Verify Orthogonal Design Problems in a Neural Processing Unit (NPU)
14:45 - 15:15	Analog Devices Presentation - Maximizing Superlint for FSM Checks and Multiple DUT Configuration Using Multimode
15:15 - 15:45	Tea Break & Poster Presentations
15:45 - 16:30	Cadence Technology Shorts
16:30 - 16:45	Closing Ceremony and Awards

Gallery Section

A showcase of stunning visuals in one place.